Related component

Sparselogic: what it is, and what it is not

A Verilog-to-FPGA synthesis service in this repo. It is not a memory system and not a non-von-Neumann fabric.

What the code actually does

cain-microservices/sparselogic-compiler takes Verilog source and drives yosys and nextpnr to produce a real FPGA bitstream for iCE40, ECP5 and Gowin targets. It requires a pin constraint file for Gowin, validates the module name, caps source size at 200 KB, and authorises synthesis through ActionProof before running a toolchain. Its tests assert that a real bitstream is produced for each target.

What the README used to claim

The README described a Python-to-FPGA pipeline with “logic mass” calculation, Prim's minimum spanning tree dependency ordering, “wormhole discovery” over imports/AST/control flow, and a 16-dimensional HNSW-lite vector index for program retrieval.

None of that is in the source. src/sparselogic_compiler/ contains only main.py (HTTP surface) and synthesis.py (the yosys/nextpnr driver). The README has been corrected to match the code rather than the other way round.

Why it is not on the memory page

• “Wormhole” in the old README meant a graph shortcut edge in a dependency graph, not anything moving over a bridge. There is no bridge and no travel-time metric in the code.
• A synthesis toolchain is not a memory system. MemoryMesh and AETHER-33 are the memory stack.
• FPGA gateware is reconfigurable hardware. Calling it “non-von-Neumann” is a category claim the code does not support and this site does not make.
• No bitstream was measured on this host: yosys and nextpnr-* are not installed, so the synthesis tests cannot run here. That is stated rather than papered over.

What would make it publishable

Install the toolchain, run the five synthesis tests, record which targets produced a bitstream and at what frequency, and publish that. Real numbers from a real compiler beat an architecture diagram every time.